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Fabrication and characterization of self-assembled and self-aligned SOI-based single-electron transistors
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<p>We present a novel technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as<br>conducting islands making use of a combination of self-assembly and self-alignment effects (for an overview of the<br>fabrication process, see Fig. 1). Starting from an ultra-thin silicon-on-insulator (SOI) substrate we employ aminosilane<br>molecules as an adhesion agent to self-assemble gold colloidal particles in a sub-monolayer [1]. These particles are then<br>used as an etch mask for a CF<sub>4</sub> reactive ion etch (RIE) process in which the silicon layer is removed everywhere except<br>below the gold colloids, yielding silicon QDs on a SiO<sub>2</sub> insulating layer. A metal wire together with symmetric side gate<br>electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample, and a nanometer-sized gap is<br>created in these wires by a controlled electromigration process [2]. Self-alignment of the evolving nano-electrodes with<br>respect to the QDs is achieved, because the metal layer is locally dilated by the QDs resulting in a locally higher current<br>density. Therefore the metal wires will preferentially break at the positions of the QDs. To obtain tunneling contacts the<br>native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can be adjusted in a controlled<br>manner by self-limiting thermal oxidation [3] to obtain an accurate tunneling resistance.<br>The devices are electrically characterized at liquid helium temperature by applying a source-drain voltage and<br>measuring the current. The I(V)-curves (Fig. 2) show clear Coulomb blockade behavior and Coulomb staircase features.<br>When the source-drain voltage is kept at a constant value and the gate voltage is varied, conductance oscillations<br>become visible. By collecting I<sub>SD</sub>(V<sub>SD</sub>)-traces for different gate voltages and calculating their numerical derivatives a so-<br>called stability diagram is obtained, exhibiting Coulomb diamonds which are typical for SETs.<br></p>
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The website of Coburg University of Applied Sciences was translated using translation software provided by a third-party provider such as DeepL. The official text is the German version of the website. No liability is assumed, either explicitly or implicitly, for the accuracy, reliability, or correctness of the translations into another language.

Fabrication and characterization of self-assembled and self-aligned SOI-based single-electron transistors

We present a novel technique to fabricate single-electron transistors (SETs) with silicon quantum dots (QDs) as
conducting islands making use of a combination of self-assembly and self-alignment effects (for an overview of the
fabrication process, see Fig. 1). Starting from an ultra-thin silicon-on-insulator (SOI) substrate we employ aminosilane
molecules as an adhesion agent to self-assemble gold colloidal particles in a sub-monolayer [1]. These particles are then
used as an etch mask for a CF4 reactive ion etch (RIE) process in which the silicon layer is removed everywhere except
below the gold colloids, yielding silicon QDs on a SiO2 insulating layer. A metal wire together with symmetric side gate
electrodes is patterned by electron beam lithography (EBL) onto the QD-covered sample, and a nanometer-sized gap is
created in these wires by a controlled electromigration process [2]. Self-alignment of the evolving nano-electrodes with
respect to the QDs is achieved, because the metal layer is locally dilated by the QDs resulting in a locally higher current
density. Therefore the metal wires will preferentially break at the positions of the QDs. To obtain tunneling contacts the
native oxide layer covering the silicon QDs is used as a tunneling barrier. Its thickness can be adjusted in a controlled
manner by self-limiting thermal oxidation [3] to obtain an accurate tunneling resistance.
The devices are electrically characterized at liquid helium temperature by applying a source-drain voltage and
measuring the current. The I(V)-curves (Fig. 2) show clear Coulomb blockade behavior and Coulomb staircase features.
When the source-drain voltage is kept at a constant value and the gate voltage is varied, conductance oscillations
become visible. By collecting ISD(VSD)-traces for different gate voltages and calculating their numerical derivatives a so-
called stability diagram is obtained, exhibiting Coulomb diamonds which are typical for SETs.

Titel:

Fabrication and characterization of self-assembled and self-aligned SOI-based single-electron transistors

Veröffentlichungsdatum:

24.02.2007

Publikationsart:

Wissenschaftliche Poster

Forschungsschwerpunkt:

Medien:

Trends in Nanoscience 2007 (Kloster Irsee)

DOI:

Weblink:

Heft:

Band:

Artikelnummer:

ISBN:

Autoren:

Conrad Wolf, Klaus Thonke, Rolf Sauer

Medien:

Trends in Nanoscience 2007 (Kloster Irsee)

Herausgeber:

Seiten:

Open Access:

Peer reviewed:

Nein

Zitierung:

Wolf, Conrad R.; Thonke, Klaus; Sauer, Rolf (2007): Fabrication and characterization of self-assembled and self-aligned SOI-based single-electron transistors. Trends in Nanoscience 2007 (Kloster Irsee).

Autoren:

Conrad Wolf, Klaus Thonke, Rolf Sauer